(1) Field of the Invention
The present invention relates to methods for fabricating a semiconductor device, and more particularly relates to a method for forming gate stacks including gate electrodes of an N-channel transistor and a P-channel transistor having separate work functions.
(2) Description of Related Art
In recent years, with increases in degree of integration, functionality and operating speed of semiconductor integrated circuit devices, a technology has been suggested in which a high-k insulating film (a high dielectric insulating film) having a higher dielectric constant than SiO2 is used as a gate insulating film.
Use of a high-k insulating film as a gate insulating film permits the formation of a relatively thick gate insulating film while a high electric field is applied below a gate. This can reduce the gate leakage current.
However, when a high-k insulating film is used as a gate insulating film and a conventionally used polysilicon electrode is used as an electrode to be formed on the gate insulating film, the threshold voltage Vt is disadvantageously increased due to a phenomenon called Fermi level pinning. Furthermore, when polysilicon is used as a material of a gate electrode, the gate capacity is reduced due to a gate depletion phenomenon. Thus, a high electric field cannot be applied below the gate, resulting in a reduction in the driving capability of a transistor.
To cope with the above, a technology has been suggested in which, instead of conventionally used polysilicon, a metal gate is used as a gate electrode. When a metal gate is used instead of polysilicon, the metal gate needs to have an independent work function for an associated one of an N-channel transistor and a P-channel transistor. To satisfy the need, a material suitable for the polarity of each transistor needs to be used. A different process flow from that when polysilicon is used is required.
A known fabrication method for a semiconductor device in which a metal gate and a high-k insulating film are used as a gate electrode and a gate insulating film, respectively, will be described hereinafter with reference to the drawings.
FIGS. 15A through 15D, 16A through 16D, and 17A and 17B are cross-sectional views for explaining essential process steps in a known fabrication method for a semiconductor device in a sequential order. It is assumed that in each figure, the left half region of the cross-sectional view when viewed from the front of the paper is an N-channel transistor formation region A and the right half region of the cross-sectional view when viewed from the front of the paper is a P-channel transistor formation region B.
As shown in FIG. 15A, a shallow trench isolation (STI) region 2 is formed in a silicon substrate 1 to define element formation regions, and then a high-k insulating film 3 is formed to cover the silicon substrate 1 and the STI region 2. Subsequently, a silicon dioxide film (SiO2) 4 serving as a sacrificial layer is formed on the high-k insulating film 3. Next, a resist pattern 5 is formed to cover a region of the silicon dioxide film 4 corresponding to the N-channel transistor formation region A.
Next, as shown in FIG. 15B, the silicon dioxide film 4 is partially etched away by wet etching using the resist pattern 5 as a mask without etching the underlying high-k insulating film 3. Subsequently, the resist pattern 5 is removed.
Next, as shown in FIG. 15C, a metal film 6 having a work function close to the band edge of a P-channel transistor is deposited on the entire silicon substrate 1 region.
Next, as shown in FIG. 15D, a resist pattern 7 is formed to cover a region of the metal film 6 corresponding to the P-channel transistor formation region B.
Next, as shown in FIG. 16A, the metal film 6 is partially etched away using the resist pattern 7 as a mask.
Next, as shown in FIG. 16B, the resist pattern 7 is removed, and then the silicon dioxide film 4 is further removed by wet etching.
Next, as shown in FIG. 16C, a metal film 8 is deposited to cover the high-k insulating film 3 and the metal film 6.
Next, as shown in FIG. 16D, resist patterns 9 are formed on both the N-channel transistor formation region A and the P-channel transistor formation region B to form gate patterns.
Next, as shown in FIG. 17A, the metal films 6 and 8 are partially removed by etching using the resist patterns 9.
Next, as shown in FIG. 17B, after the resist patterns 9 are removed, a gate pattern formed of one of the remaining parts of the metal film 8 is formed on the N-channel transistor formation region A, and a gate pattern formed of the remaining part of the metal film 6 and the other remaining part of the metal film 8 is formed on the P-channel transistor formation region B.
As described above, according to the known fabrication method for a semiconductor device, a dual metal gate structure is formed through the above-mentioned process steps.
Meanwhile, according to the known fabrication method for a semiconductor device, as described above with reference to FIG. 15B, the silicon dioxide film 4 serving as a sacrificial layer is removed by wet etching. Therefore, a photoresist to be used is limited, and thus it is difficult to control the positioning of the border between the N-channel transistor formation region A and the P-channel transistor formation region B. Furthermore, since it is difficult to selectively remove the silicon dioxide film 4 on the high-k insulating film 3, damage is more likely to be caused to the high-k insulating film 3 serving as an underlayer for the silicon dioxide film 4.
Furthermore, as shown in FIG. 17B, the gate pattern formed on the N-channel transistor formation region A and formed of the part of the metal film 8 and the gate pattern formed on the P-channel transistor formation region B and formed of the part of the metal film 6 and the part of the metal film 8 have different heights. For this reason, the size of each channel transistor is hardly controlled with accuracy without causing damage to the gate insulating film 3 serving as an underlayer for etching.